Power device packages and methods of fabricating the same

ABSTRACT

Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.10-2007-0119309, filed on Nov. 21, 2007 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power device packages and methods ofmanufacturing the same, and more particularly, to power device packagesincluding a plurality of stacked power semiconductor chips, and methodsof manufacturing such power device packages.

2. Description of the Related Art

Recent developments in power electronics including such power devices asservo drivers, inverters, silicon-controlled rectifiers (SCRs) andconverters are leading to manufacturing light and small power deviceswith excellent performance characteristics. Related researches are beingactively conducted into smart or intelligent power modules in which avariety of power semiconductor chips and low power semiconductor chipssuch as IC chips for controlling the power semiconductor chips, can beintegrated into one package.

In the conventional art, a plurality of semiconductor chips areindividually mounted in die attach regions of a substrate in order tomanufacture a plurality of semiconductor chips into one package.However, since the footprint area of the conventional power devicepackage is increased as the number of mounted semiconductor chipsincreases, a desired compact power device package cannot be obtained. Inaddition, as the volume of the conventional power device package isincreased, its electrical and mechanical reliability may be readilydeteriorated due to temperature cycles that are repeated in a range ofhigh temperature, and the life span of the power device package may beshorted.

Therefore, a stacked power device package, in which stacked powersemiconductor chips are mounted on a substrate, has recently beensuggested to minimize the footprint area and volume of the power devicepackage. However, the cost for manufacturing the stacked power devicepackage is relatively high because the wiring process for electricalconnection between the stacked power semiconductor chips is complicatedand expensive. Also, since vertical type power semiconductor devicessuch as insulated-gate bipolar transistors (IGBTs),metal-oxide-semiconductor (MOS) transistors, power diodes, powerregulators, etc. use a lower surface of semiconductor chips as a drainelectrode or a ground electrode, it is difficult to stack the powerdevice chips into a power device package.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention provide power device packages in whicha wiring process for electric connection between stacked powersemiconductor chips can be simplified, wherein the stacked power devicepackages have excellent compatibility with power semiconductor chipswhose lower surface is used as electrodes, and the electric andmechanical characteristics of the power device packages cannot be easilydeteriorated due to heat during the operation thereof.

Aspects of the present invention also provide methods of manufacturingthe power device packages having the above-described advantages at lowcost.

According to an aspect of the present invention, an exemplary powerdevice package comprises a substrate including at least one first dieattach region, at least one first power semiconductor chip and at leastone second power semiconductor chip stacked in order on the first dieattach region, and at least one die attach paddle disposed between theat least one first power semiconductor chip and the at least one secondpower semiconductor chip. The die attach paddle comprises an adhesivelayer that is attached to a top surface of the first power semiconductorchip, a conductive pattern, and an interlayer member between theadhesive layer and the conductive pattern. The conductive patternincludes a second die attach region, on which the second semiconductorchip is mounted, and a wire bonding region that is electricallyconnected to the second die attach region. The exemplary power devicepackage further comprises a plurality of first leads electricallyconnected to at least one of the at least one first power semiconductorchip and the at least one second power semiconductor chip.

In some embodiments, the adhesive layer of the die attach paddle mayinclude a resin-based epoxy, a paste, and/or an adhesive tape. Theconductive pattern of the die attach paddle may include a copper layer.

The second die attach region and the wire bonding region of the paddle'sconductive pattern may be electrically connected to each other. In someembodiments, the conductive pattern may comprise a gap to separate atleast a portion of the second die attach region and at least a portionof the wire bonding area from each other. The lower surface of a secondpower semiconductor chip attached to the die attach region may functionas an electrode.

In some embodiments, the wire bonding region of the die attach paddlemay be electrically connected to one of the first leads or to theconductive pattern on the substrate via a first wire. The die attachpaddle may be disposed so as to expose a connection pad of the firstpower semiconductor chip, and the connection pad of the first powersemiconductor chip and a connection pad of the second powersemiconductor chip may be electrically connected via a second wire. Theconnection pad of the second power semiconductor chip may beelectrically connected to the first lead or to the conductive pattern onthe substrate via a third wire. In some embodiments, the second wire andthe third wire may be provided by one stitch bonded wire.

According to another aspect of the present invention, an exemplarymethod of manufacturing a power device package comprises obtaining a dieattach paddle substrate including an interlayer member layer and aconductive pattern formed on the interlayer member layer; attaching anadhesive layer to a surface of the interlayer member layer opposite tothe conductive pattern; forming a die attach paddle by singulating thedie attach paddle substrate and the adhesive layer; attaching theadhesive layer of the die attach paddle to a top surface of the firstpower semiconductor chip mounted on the first die attach region on thesubstrate; and attaching a lower surface of the second powersemiconductor chip to a second die attach region of the die attachpaddle. The singulation process is known in the semiconductor art and isthe process where one or more components, which are initially part of alarger entity such as a substrate or wafer, are separated from thelarger entity and made into individual entities. As used herein, theaction of “singulating” a component (e.g., the die attach paddle) meansseparating the component from the larger entity (e.g., the die attachpaddle substrate and the adhesive layer), and the action of“singulating” a larger entity (e.g., the die attach paddle substrate andthe adhesive layer) means separating one or more individual components(e.g., the die attach paddle) from the larger entity.

In some embodiments, the conductive pattern of the die attach paddle maycomprise a plurality of patterns separated apart from one another. Theforming of the die attach paddle may comprise cutting the interlayermember layer and the adhesive layer between the patterns. The adhesivelayer may be provided together with a detachable base film for handlingthe die attach paddle, with the base film being detachably attached(e.g., lightly adhered) to the adhesive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a perspective view of a power device package according to anembodiment of the present invention;

FIG. 2A is a cross-sectional view of the power device package of FIG. 1cut along a line IIa-IIa;

FIG. 2B is a cross-sectional view of the power device package of FIG. 1cut along a line IIb-IIb);

FIG. 3 is a cross-sectional view illustrating a power device packageaccording to another embodiment of the present invention;

FIGS. 4A through 4D are plane views illustrating a method ofmanufacturing a die attach paddle in process flows according to anembodiment of the present invention;

FIGS. 5A through 5D are cross-sectional views of the die attach paddlecut along corresponding cutting lines, Va-Va and Vb-Vb, of FIGS. 4Athrough 4D; and

FIG. 6 is a cross-sectional view illustrating a method of attaching thedie attach paddle according to an embodiment of the present inventiononto a first power semiconductor chip.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments according tothe invention are shown.

The invention may, however, be embodied in many different forms andshould not be construed as being limited to the embodiments set forthherein; rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the concept of theinvention to those skilled in the art.

It will also be understood that when a layer is referred to as being“on” another layer or substrate, it can be directly on the other layeror substrate, or intervening layers may also be present. In thedrawings, the thicknesses and sizes of layers and regions areexaggerated for clarity, and like reference numerals in the drawingsdenote like elements. It will also be understood that when an element,such as a layer, a region, or a substrate, is referred to as being “on,”“connected to,” “electrically connected to,” “coupled to,” or“electrically coupled to” another element, it may be directly on,connected or coupled to the other element, or one or more interveningelements may be present. In contrast, when an element is referred to asbeing “directly on,” “directly connected to” or “directly coupled to”another element or layer, there are no intervening elements or layerspresent. The term “and/or” used herein includes any and all combinationsof one or more of the associated listed items.

The terms used herein are for the purpose of illustrating the presentinvention only and should not be construed to limit the meaning or thescope of the present invention. As used in this specification, asingular form may, unless definitely indicating a particular case interms of the context, include a plural form. Also, the expressions“comprise” and/or “comprising” used in this specification neither definethe mentioned shapes, numbers, steps, operations, members, elements,and/or groups of these, nor exclude the presence or addition of one ormore other different shapes, numbers, steps, operations, members,elements, and/or groups of these, or addition of these. Spatiallyrelative terms, such as “over,” “above,” “upper,” “under,” “beneath,”“below,” “lower,” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device (e.g., package) in use or operationin addition to the orientation depicted in the figures. For example, ifthe device in the figures is turned over, elements described as “below”or “beneath” or “under” other elements or features would then beoriented “over” or “above” the other elements or features. Thus, theexemplary term “above” may encompass both an above and beloworientation.

As used herein, terms such as “first”, “second”, etc. are used todescribe various members, components, regions, layers, and/or portions.However, it is obvious that the members, components, regions, layers,and/or portions should not be defined by these terms. The terms are usedonly for distinguishing one member, component, region, layer, or portionfrom another member, component, region, layer, or portion. Thus, a firstmember, component, region, layer, or portion which will be described mayalso refer to a second member, component, region, layer, or portion,without departing from the scope of the present invention.

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments according tothe invention are shown. In the drawings, modification of theillustrated shapes may be expected according to the manufacturingtechnique and/or tolerance in the drawings. Accordingly, the embodimentsaccording to the present invention should not be construed as beinglimited to the particular forms in the illustrated drawings, and shouldinclude changes in the shape caused during the manufacturing process.

FIG. 1 is a perspective view illustrating a power device package 1000according to an embodiment of the present invention. FIG. 2A is across-sectional view of the power device package of FIG. 1 cut along aline IIa-IIa. FIG. 2B is a cross-sectional view of the power devicepackage of FIG. 1 cut along a line IIb-IIb. In FIG. 1, a molding member700 is omitted for convenience of explanation; however, the moldingmember 700 is completely disclosed in FIGS. 2A and 2B.

Referring to FIGS. 1, 2A, and 2B, the power device package 1000 mayinclude first power semiconductor chips 200 a, 200 b, and 200 c andsecond power semiconductor chips 300 a, 300 b, and 300 c that arestacked on a first die attach region 110 a of a substrate 100. The firstand second power semiconductor chips 200 a, 200 b, 200 c, 300 a, 300 b,and 300 c may comprise metal-oxide-semiconductor field-effecttransistors (MOSFETs), bipolar junction transistors (BJTs),insulated-gate bipolar transistors (IGBTs), diode devices, and/or otherpower-handling devices for controlling electrical power in such devicesas servo drivers, inverters, power regulators, and converters, and soon. Connection pads 210 and 310 of the stacked first and second powersemiconductor chips 200 a, 200 b, 200 c, 300 a, 300 b, and 300 c areelectrically interconnected via first wires 611, 612, 613, second wires621, 622, 623, third wires 631, and fourth wires 641, 642. These wiresare described below in greater detail.

In some embodiments according to the present invention, the size of thesecond power semiconductor chips 300 a, 300 b, and 300 c that aremounted on the first power semiconductor chips 200 a, 200 b, and 200 cmay be smaller than the size of the first power semiconductor chips 200a, 200 b, and 200 c. For example, the first power semiconductor chips200 a and 200 c may comprise transistors such as MOSFETs, BJTs, and/orIGBTs, and the second power semiconductor chips 300 a and 300 c maycomprise diodes that are smaller than the transistors. However, this ismerely an example, and other configurations are also possible. Forexample, the first power semiconductor chip 200 b may be a large-sizedMOSFET having a large current capacity, and the second powersemiconductor chip 300 b may be a small-sized MOSFET having a smallcurrent capacity.

Regarding the stacking configuration of the first and second powersemiconductor chips, one second power semiconductor chip 300 a or 300 bmay be stacked on one first power semiconductor chip 200 a or 200 b byusing one die attach paddle 400 a or 400 b. Alternatively, a pluralityof second power semiconductor chips 300 c, such as two such chips, maybe stacked on a first power semiconductor chip 200 c having a largecurrent capacity, by using one or more die attach paddles 400 c (the useof two die attach paddles 400 c is shown in FIG. 2B).

The stacking configuration of the first power semiconductor chips 200 a,200 b, 200 c and the second power semiconductor chips 300 a, 300 b, 300c may include various combinations of the stacking configurationdisclosed by FIG. 1. Although not illustrated in FIG. 1, it is wellunderstood that a power device package in which another die attachpaddle is attached to the second power semiconductor chips 300 a, 300 b,and 300 c and third power semiconductor chips are stacked on the dieattach paddle, may also be included in the embodiments according to thepresent invention. Also, a power device package in which one die attachpaddle is attached to a plurality of first power semiconductor chips andone or more second power semiconductor chips are stacked on the dieattach paddle, may be included in the embodiments according to thepresent invention.

Hereinafter, the substrate 100 and the die attach paddle 400 a, 400 b,and 400 c will be described in detail. The substrate 100 may comprise aninsulating substrate on which a conductive pattern 110 is formed.Conductive pattern 110 may comprise appropriate regions 110 a and 110 b,some of which (e.g., regions 110 b) may be electrically conductive andsome of which (e.g., regions 110 a) may not be electrically conductive.The insulating substrate may comprise, for example, a printed circuitboard (PCB), a flexible PCB (FPCB), an insulated metal substrate (IMS),a pre-molded substrate, or a direct bonded copper (DBC) substrate.However, these are just examples of the substrate, and the substrate ofthe present invention is not limited thereto. For example, the substrate100 may comprise a conductive substrate provided by a lead frame.

The conductive pattern 110 of the substrate 100 may provide a first dieattach region 110 a, on which the first power semiconductor chips 200 a,200 b, and 200 c are mounted, and a interconnection region 110 b that iselectrically bonded to a wire and/or lead. When the first die attachregion 110 a is electrically conductive, a bottom surface of the firstpower semiconductor chips 200 a, 200 b, and 200 c may be bonded to thefirst die attach region 110 a by using an electrically conductiveadhesive layer, for example, solder or a metal epoxy, to provide anelectrical connection between die attach region 110 a and the chip 200.If an electrical connection is not needed, then any adhesive layer maybe used. In the embodiments, the first die attach region 110 a is notlimited to being electrically conductive. When first die attach region110 a is not electrically conductive, a chip 200 may be attached to itusing any type of adhesive.

In some embodiments, a metal layer 150 may be disposed on a lowersurface of the substrate 100 in order to increase the heat dissipationefficiency of the power device package 1000. The metal layer 150 may beexposed to the outside of the molding member 700 and coupled to anexternal heat sink (not shown).

Die attach paddles 400 a, 400 b, and 400 c are attached to the firstpower semiconductor chips 200 a, 200 b, and 200 c to stack the secondpower semiconductor chips 300 a, 300 b, and 300 c. The die attachpaddles 400 a, 400 b, and 400 c include an adhesive layer 410, aconductive pattern 420, and an interlayer member 430 between theadhesive layer 410 and the conductive pattern 420. The adhesive layers410 are attached to a top surface of the first power semiconductor chips200 a, 200 b, and 200 c. The adhesive layers 410 may comprise, forexample, a resin-based epoxy, a paste, and/or an adhesive tape havingexcellent thermal resistance, and the adhesive layer 410 may benon-conductive. In some embodiments according to the present invention,the adhesive tape may comprise a high temperature tape that comprises awell-known glass tape, silicone tape, teflon tape, stainless foil tape,ceramic tape, and so forth. The thickness of the adhesive layer 410 maybe, for example, 5-300 μm (microns).

The conductive pattern 420 of each die attach paddle 400 a-400 cincludes a second die attach region 421 on which a lower surface of asecond power semiconductor chip 300 a-300 c may be mounted, and a wirebonding region 422 that is electrically connected to the second dieattach region 421. The conductive pattern 420 may include an aluminumlayer, a copper layer, and/or an alloy layer thereof. When theconductive pattern 420 includes a copper layer, a well-known oxidationprevention layer, for example, a nickel layer or a gold layer, may beplated over the copper layer to prevent oxidation.

As illustrated in FIG. 1, the second die attach region 421 and the wirebonding region 422 may be electrically connected to each other by oneconductive pattern 420. If necessary, the second die attach region 421and the wire bonding region 422 may be realized as separate conductivepatterns, and they may be electrically connected to each other by usinga conductive connection member, such as a wire.

The lower surface of the second power semiconductor chips 300 a, 300 b,and 300 c may be attached to the second die attach regions 421 of thedie attach paddle 400 a, 400 b, and 400 c. The lower surface of thesecond power semiconductor chips 300 a, 300 b, and 300 c and the seconddie attach regions 421 may be attached using respective conductiveadhesive members 350, which may comprise solder, a metal epoxy, aconductive paste, conductive tape, and so forth.

When coating a conductive adhesive member 350 on the second die attachregion 421 or when pressing the second power semiconductor chips 300 a,300 b, and 300 c onto the second die attach regions 421 (such as beforeattaching the chips 300 with a reflow operation), the conductiveadhesive member 350 may leak out around the second power semiconductorchip 300 a, 300 b, and 300 c. The leaked adhesive member 350 may intrudeinto the adjacent bonding region 422, and this may impede a wire bondingprocess which is to be described later.

In order to prevent the leakage of the adhesive member 350, in someembodiments according to the present invention, a gap 423 may be formedin the conductive pattern 420, and the gap 423 separates the second dieattach region 421 and a portion or the whole of the wire bonding region422. In this case, a surface of the interlayer member 430 may be exposedby the gap 423. Even if the adhesive member 350 is leaked around thesecond power semiconductor chips 300 a, 300 b, and 300 c, the leakedadhesive member 350 is prevented from extending to the wire bondingregion 422 by the gap 423. The shape of the gap 423 may vary. Forexample, the gap 423 may be formed to define an opening in the form of aslit (not shown), which has a predetermined width and length, instead ofhaving one opened end as illustrated in FIG. 1.

Alternatively, in order to prevent extension of the adhesive member 350,a leakage preventing structure such as a dam may be provided around thesecond die attach region 421. Alternatively, the second die attachregion 421 and the wire bonding region 422 may each be formed ofdifferent materials, or the wire bonding region 422 may be formed tohave a greater thickness than the second die attach region 421, therebyproviding a step barrier.

In the die attach paddles 400 a, 400 b, and 400 c according to thecurrent embodiment, an interlayer member 430 that separates the adhesivelayer 410 and a conductive pattern 420 may be electrically insulating.For example, the interlayer member 430 may comprise a ceramic, apolymer, and/or an insulated metal substrate. That is, the interlayermember 430 may provide, together with the conductive pattern 420thereon, a substrate on which the second power semiconductor chips aremounted and that can be wire-bonded, such as a PCB, a flexible PCB, aninsulated metal substrate (IMS), a pre-molded substrate or a directbonded copper (DBC) substrate. These are just examples of the substrate,and the present invention is not limited to these substrates.

In some embodiments according to the present invention, the size of thedie attach paddles 400 a, 400 b, and 400 c may be smaller than the sizeof the underlying first power semiconductor chips as illustrated inFIGS. 1, 2A, and 2B. For example, the die attach paddles 400 a, 400 b,and 400 c may have a size that is sufficient to expose the connectionpads 210 of the first power semiconductor chips 200 a, 200 b, and 200 cfor wire bonding, and that is sufficient to provide the second dieattach regions 421 and the wire bonding regions 422 for the second powersemiconductor chips 300 a, 300 b, and 300 c thereon.

The stacked first power semiconductor chips 200 a, 200 b, and 200 c andthe second power semiconductor chips 300 a, 300 b, and 300 c may beelectrically connected to a plurality of first leads 510, the connectionpads 210, and the wiring regions 110 b on the substrate 100 for thefirst and second power semiconductor chips 200 a, 200 b, 200 c; 300 a,300 b, and 300 c, via first wires 611, 612, 613, second wires 621, 622,623, third wires 631, and fourth wires 641, 642, as described below ingreater detail. Hereinafter, as shown in FIGS. 2A and 2B, wires 611,612, 613, 621, 622, 623, 631, 641, and 642, will be described, withrespect to a case where the first power semiconductor chips 200 a and200 c comprise bipolar transistors and the second power semiconductorchips 300 a and 300 c comprise diodes. However, the connectingconfiguration of the bipolar transistors, the diodes, and the wires isan example, and the embodiments according to the present invention arenot limited thereto. The wires 611, 612, 613, 621, 622, 623, 631, 641,and 642 may be well-known power supply wires such as aluminum wires, andmay have diameters of 5-20 mils to sustain high levels of current. Thebonding process of the wires may be performed using a ball bondingprocess, a wedge bonding process, a stitch bonding process, and/or otherknown bonding processes.

The connection pad 210, such as a source and/or emitter connection padthat is provided on the first power semiconductor chip 200 a, may beelectrically connected to a interconnection region 110 b of thesubstrate 100 by using a first wire 611 and/or to a connection pad 310of the second power semiconductor chip 300 a by using a second wire 621,as illustrated in FIG. 2A. In other embodiments, the connection pad 210of the first power semiconductor chip 200 c may be electricallyconnected to one of first leads 510 or the wire bonding region 422 ofthe die attach paddle 400 c by first wires 612 and 613, as illustratedin FIG. 2B.

The anode connection pad 310 that is provided on the second powersemiconductor chip 300 a may be electrically connected to the connectionpad 210 of the first power semiconductor chip 200 a by using the secondwire 621, as illustrated in FIG. 2A, and to the first lead 510 by usinga third wire 631. In some embodiments, at least two of the first,second, and third wires 611, 621, 631 may be realized as one continuouswire. For example, the electric connection may be performed by using onewire and a stitch bonding method such as a wire 650 illustrated inFIG. 1. Also, the connection pad 310 of the second power semiconductorchip 300 c may be electrically connected to the lead 510 or the wiringregion 110 b of the substrate 100 by using second wires 622 and 623, asillustrated in FIG. 2B.

The wire bonding region 422 of the die attach paddle 400 a may beelectrically connected to the first die attach region 110 a on thesubstrate 100 by using a fourth wire 641, as illustrated in FIG. 2A, sothat the lower surface of the first power semiconductor chip 200 a, forexample a drain electrode of a transistor, and the lower surface of thesecond power semiconductor chip 300 a, for example a cathode of a diode,may have the same potential. Another fourth wire 642 may be connected toeither of the interconnection regions 110 b of the substrate 100 and one(not shown) of the first leads 510, as may be needed by the circuit.

FIG. 3 is a cross-sectional view illustrating a power device package2000 according to another embodiment of the present invention. Among theelements of FIG. 3, the elements having the same reference numerals asthe elements in FIGS. 1, 2A, and 2B may be described similarly to thedescription provided with reference to FIGS. 1, 2A, and 2B.

Referring to FIG. 3, the power device package 2000 may further include acontrol chip 800 for controlling at least one of the first and secondpower semiconductor chips and a plurality of second leads 520 that areelectrically connected to the control chip 800. The control chip 800 maycomprise, for example, a micro-processor. Depending on the number of thefirst and second power semiconductor chips 200 and 300, two or morecontrol chips may be provided. By implementing the control chip 800, asmart power device including a control unit and a power unit may beprovided.

In some embodiments, the control chip 800 may be disposed on a dieattach paddle 550 on a lead frame that may be opposite to the first lead510 as shown in FIG. 3. Alternatively, although not illustrated in theFIG. 3, the control chip 800 may be disposed on the substrate 100. Thecontrol chip 800 may be electrically connected to one of second leads520 via a fifth wire 660. Also, the second lead 520 that is connected tothe control chip 800 may be electrically connected to the connection pad210 of the first power semiconductor chip 200 via a sixth wire 670. Itcan be well understood from previously-described embodiments accordingto the present invention that the second lead 520 may be electricallyconnected to the interconnection region 110 b on the substrate 100 or tothe first lead 510 according to another embodiment. The fifth wire 660and/or sixth wire 670 may comprise aluminum wire or gold wire, and mayhave a relatively small thickness of 0.8 through 3 mil. For the sixthwire 670, the above-described power supply wire may be applied.

According to the above embodiments of the present invention, as aplurality of power semiconductor chips are stacked using die attachpaddles, the footprint area of the substrate may be reduced to a sizefor mounting first power semiconductor chips. Even if the substrate isan expensive DBC substrate, economical power device packages can beprovided, since the area of the substrate is reduced. In addition, thedie attach paddle according to the embodiments of the present inventionincludes a wire bonding region and thus the lower surface of the powersemiconductor chip mounted on the die attach paddle can be used as anelectrode, and thus a difficulty in view of a wiring process can besolved.

FIGS. 4A through 4D are plane views illustrating a method ofmanufacturing a die attach paddle in the process flow; and FIGS. 5Athrough 5D are cross-sectional views of the die attach paddle cut alongcorresponding cutting lines, Va-Va and Vb-Vb, of FIGS. 4A through 4D.

Referring to FIGS. 4A and 5A, a die attach paddle substrate 400S thatincludes an interlayer member layer 430L and a conductive pattern 420 onthe interlayer member layer 430L may be obtained. Die attach paddlesubstrate 400S may be obtained by manufacturing it according to knownmanufacturing processes, or by receiving it from a vendor that hasmanufactured it according to aspects of the present invention usingknown manufacturing processes. In some embodiments, the conductivepattern 420 may include a plurality of patterns that are alreadypatterned and separated apart from each other, such as at predetermineddistances L1 and L2. Each of the patterns may include a die attachregion 421 and a wire bonding region 422.

Referring to FIGS. 4B and 5B, an adhesive layer 410L is attached to asurface of the interlayer member layer 430L that is opposite to theconductive pattern 420 by coating, heating, and/or pressing the adhesivelayer 410L. In some embodiments, the adhesive layer 410L may be providedwith a detachable base film (BL) as a means for handling the die attachpaddle; the base film (BL) is detachably attached (e.g., lightlyadhered) to the adhesive layer 410L. The base film (BL) may comprise,for example, a dicing tape that is commonly used in a chip singulationprocess. Also, a handler (not shown) may be attached around the dicingtape in order to facilitate a handling operation.

Referring to FIGS. 4C and 5C, by using a laser, a blade, or a saw thatis widely used in semiconductor manufacturing processes, the die attachpaddle substrate 400S and the adhesive layer 410L are singulated to formone or more instances of a die attach paddle 400. The singulationprocess is known in the semiconductor art and is the process where oneor more components, which are initially part of a larger entity such asa substrate or wafer, are separated from the larger entity and made intoindividual entities. As used herein, the action of “singulating” acomponent means separating the component from the larger entity, and theaction of “singulating” a larger entity means separating one or moreindividual components from the larger entity. When the conductivepattern 420 is formed of a plurality of separated patterns, such asdescribed above, the singulation process can be performed bycontinuously cutting the interlayer member layer 430L and the adhesivelayer 410L between the conductive patterns 420.

Referring to FIGS. 4D and 5D, the singulated die attach paddle 400 isseparated from the base film (BL) using a pick-up method using a vacuumabsorption method, for example. In order to separate the die attachpaddle 400, a die bonder (DB) which is used in semiconductor packagingmay be used.

FIG. 6 is a cross-sectional view illustrating a method of attaching thedie attach paddle 400 onto a first power semiconductor chip 200.Referring to FIG. 6, the adhesive layer 410 of the die attach paddle 400is attached to a top surface of the first power semiconductor chip 200that is mounted on the substrate 100. In order to attach the adhesivelayer 410, heat and/or pressure may be applied to the adhesive layer 410through the die bonder DB. Then, the lower surface of the second powersemiconductor chip is attached to the second die attach region 421 ofthe die attach paddle 400. In order to attach the lower surface of thesecond power semiconductor chip to the second die attach region 421, asolder, a metal epoxy, or a conductive paste may be coated on the seconddie attach region 421, or a conductive tape may be attached on the lowersurface of the second power semiconductor chip.

Also, as described above with reference to FIG. 3, in order to provide asmart power module, a control chip may be further mounted on a paddle ofa lead frame. Then, a wire bonding process that is appropriate forelectrically connecting the first and second semiconductor chips isperformed. When the wire bonding process is completed, the substrate istransferred to a molding apparatus, and a transfer molding process isperformed, in which a molding member 700 for protecting componentsinside the power semiconductor package is formed. Then, as is well-knownin the art, a subsequent process, such as a trimming process forseparating leads from one another and forming process, is performed.

According to embodiments of the present invention, a compact powerdevice package can be provided by reducing the footprint area of asubstrate by stacking a plurality of power semiconductor chips by usingdie attach paddles. Also, in cases where the lower surface of the powersemiconductor chip mounted on the die attach paddle can function as adrain electrode, electrical connection between the wire bonding regionand the drain electrode is enabled by the bonding region of the dieattach paddle, and thus difficulties in the wiring process can besolved. In addition, according to embodiments of the present invention,the total volume of the power device package is reduced and thusdeformation due to a heat expansion of the package components, such asthe substrate and the molding member, can be reduced, and thus aproblem, such as reduction in the life span of the power device packagedue to repeated high temperature cycles, can be solved.

Also, since the power device package according to embodiments of thepresent invention is manufactured by stacking the power semiconductorchips by using a singulation process and a pick-up process using a laseror a saw which are widely used in semiconductor device manufacturingprocesses, the power device package according to embodiments of thepresent invention can be manufactured at low cost.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1-17. (canceled)
 18. A method of manufacturing a power device package,the method comprising: obtaining a die attach paddle substrate includingan interlayer member layer and a conductive pattern formed on theinterlayer member layer; attaching an adhesive layer to a surface of theinterlayer member layer opposite to the conductive pattern; forming adie attach paddle by singulating the die attach paddle substrate and theadhesive layer; attaching the adhesive layer of the die attach paddle toa top surface of the first power semiconductor chip mounted on the firstdie attach region on the substrate; and attaching a lower surface of thesecond power semiconductor chip to a second die attach region of the dieattach paddle.
 19. The method of claim 18, wherein the conductivepattern of the die attach paddle substrate comprises a plurality ofpatterns separated apart from one another.
 20. The method of claim 18,wherein the forming of the die attach paddle comprises cutting theinterlayer member layer and the adhesive layer between the patterns. 21.The method of claim 18, wherein the die attach paddle substratecomprises a detachable base film detachably attached to the adhesivelayer of the die attach paddle substrate.
 22. The method of claim 21,wherein forming the die attach paddle further comprises separating thedie attach paddle from the base film by using a pick-up method.
 23. Themethod of claim 22, wherein the pick-up method is performed using a diebonder.
 24. The method of claim 18, wherein the lower surface of thesecond power semiconductor chip and the second die attach region of thedie attach paddle are attached using a conductive adhesive member. 25.The method of claim 18, further comprising, after the attaching of thelower surface of the second power semiconductor chip, electricallyconnecting at least one of connection pads of the first powersemiconductor chip and connection pads of the second power semiconductorchip and a lead by using a wire.